1. Field of the Invention
The present invention relates to a wiring board with an embedded device and electromagnetic shielding, and more particularly to a wiring board having a shielding lid and shielding slots that can respectively serve as vertical and horizontal shields for the embedded device.
2. Description of Related Art
The semiconductor devices are susceptible to electromagnetic interference (EMI) or other inter-device interference, such as capacitive, inductive, conductive coupling when operated in a high frequency mode. These undesirable interferences may become increasingly serious when the semiconductor dies are placed closely together for the miniaturization purpose. In order to minimize the electromagnetic interference, shielding may be required on certain semiconductor devices and modules.
U.S. Pat. No. 8,102,032 to Bolognia et al., U.S. Pat. No. 8,105,872 to Pagaila et al., U.S. Pat. No. 8,093,691 to Fuentes et al., U.S. Pat. No. 8,314,486 and U.S. Pat. No. 8,349,658 to Chi et al. disclose various methods used for shielding of semiconductor devices including metal cans, wire fences, or ball fences. All of the above approaches are designed for the devices assembled on a substrate and the shielding materials such as metal cans, metal film, wire or ball fences are all external added-on which requires additional space and thus increases the footprint of the semiconductor package and the extra cost.
U.S. Pat. Nos. 7,929,313, 7,957,154 and U.S. Pat. No. 8,168,893 to Ito et al. disclose a method of using conductive via hole in a resin layer to form an electromagnetic shielding layer that surrounds a concave portion for housing an embedded semiconductor device. This structure promises a superior electrical shielding for the embedded devices at minimal space, but the conductive via which needs to be as deep as the thickness of semiconductor device suffers limitations in high aspect ratio of via drilling and via plating and can only accommodate some ultra-thin devices. Furthermore, as the concave portion which serves as the die placement area is formed after the metallization of conductive via, dislocation of semiconductor device due to poor alignment makes this method prohibitively low yield in volume manufacturing.